1. Field of the Invention
The present invention relates generally to digital signal processing, and more particularly to processing of digital signals using a logic cell suitable for a domino logic implementation.
2. State of the Art
Domino logic has achieved widespread use for integrated circuits which include regular arrays. With domino logic, a standard cell formed with a plurality of transistors represents a stage. A plurality of the stages can then be connected in series for implementing domino logic.
For example, a multi-input AND function or a multi-input OR function can be implemented using domino logic. In the case of a multi-input AND function, a two-input AND gate can be implemented as a single stage. A plurality of such stages can then be cascaded together in series to implement the multi-input AND function. A signal input to the first stage is evaluated therein, and the first stage then produces an output which propagates to the second stage where outputs of the first stage are evaluated. The second stage then produces additional outputs which in turn are propagated to the third stage wherein they are evaluated, and so on.
A significant feature of domino logic is that signals can propagate through the various stages without being separately clocked at each stage. Thus, a single clock cycle can be used to initiate the propagation of input signals through a plurality of cascaded stages which collectively represent a relatively complex function. This avoids the need for high speed clocks to implement relatively complex functions, by avoiding the need for plural clock cycles to process the signal inputs. At the same time, the evaluation of the signal inputs within a single clock cycle provides relatively fast signal processing.
Despite these advantages, domino logic has been limited in its applicability. For example, where domino logic is implemented using MOS technology, integrated circuits such as adder circuits cannot be implemented because they require the use of negative logic functions (e.g., NOR, NOT, NAND functions). On the contrary, conventional MOS implemented domino logic is limited to use of positive logic functions. As referenced herein, positive logic refers to the use of non-inverting gates to implement a function (e.g., AND, OR and so forth). Gates such as NAND, NOR or NOT gates constitute negative logic and are therefore not appropriate for use with MOS implemented domino logic.
Given the relatively low power requirements of MOS technology, efforts have been directed to cascading MOS implemented adders to achieve the features of domino logic. Accordingly, various solutions have been proposed to avoid the limits of implementing domino logic with MOS circuitry. For example, an article entitled "A 140-MHz CMOS Bit-Level Pipelined Multiplier-Accumulator Using A New Dynamic Full-Adder Cell Design", Lu et al, 1990 Symposium on VLSI circuits (Hawaii 1990), discloses the implementation of a full-adder circuit using MOS circuitry in a pipelining technique. The pipelining technique proposed by the Lu et al document does not constitute a true domino logic implementation since the disclosed circuitry requires a separate clock cycle for each cascaded stage of the circuit.
Referring to FIG. 2 of the Lu et al document, it can be seen that the pipelining technique described therein involves dissecting an addition operation into two basic functions: a first function for providing a carry output as a combination of inputs labeled Ai, Ci, and Si; and a second function for providing a sum output as a combination of the aforementioned three inputs plus an inverted carry output from the carry function. Both of these functions are implemented using MOS technology; the carry function labelled "C-block" is implemented with p-channel MOS transistors and the sum function labelled "S-block" is implemented with n-channel MOS transistors.
Despite its ability to include negative logic functions, the FIG. 2 implementation of the Lu et al document results in significant drawbacks. These drawbacks prevent implementation of domino logic using the logic cell disclosed therein.
MOS implementation of domino logic requires compliance with specific rules. For example, instabilities at the inputs of each cascaded stage can not be tolerated.
More particularly, all inputs of an n-channel stage are permitted to transition from logic 0 to logic 1 or to remain stable at their previous value (i.e., logic 0) during an evaluation phase to turn on an n-channel transistor of a subsequent cascaded stage. Any transition from logic 1 to logic 0 during the evaluation phase constitutes an illegal input signal condition for the subsequent cascaded stage. On the contrary, for a p-channel stage, all inputs are permitted to transition from a logic 1 to a logic 0 or to remain stable at their previous values (i.e., logic 1) during an evaluation stage (i.e., a 0 is required to turn on a p-channel transistor of a subsequent stage). Any transition from logic 0 to logic 1 during the evaluation phase constitutes an illegal input condition for a subsequent, cascaded p-channel stage.
To address the instabilities associated with the use of negative logic functions, a 4 transistor latch is provided at the logic cell outputs of both the S-block and the C-block in FIG. 2 of the Lu patent. Latching of the output signals So and Co stabilizes the logic condition of these output signals to provide a subsequent stage with legal input signals from a previous stage. However, both the clock signal "CLK" used for pre-charge and an inverted clock signal labeled CLK are required for gating the latch to transfer the output signals from the first stage to the subsequent stage. Further, plural clock cycles are required for propagating signals through plural cascaded stages of the Lu et al implementation. This reflects the pipeline technique used by Lu et al to propagate signals through the circuit.
This pipelining technique of the Lu et al document poses significant drawbacks to the circuit designer. For example, a relatively high speed clock (e.g., 140 MHz) is required to implement the large number of clock cycles necessary for propagating input signals through sequential stages. Further, the need for a separate clock cycle at each stage requires that the clock signal be routed to a large portion of the circuitry, thus increasing overall power requirements of the integrated circuit. Further, the increased circuitry required for the output latches and for the routing of the clock imposes serious area constraints on the overall design which lead to increased size and costs.
Accordingly, it would be desirable to provide an implementation of domino logic which is not restricted to the use of positive functions, yet which can realize significant advantages of true domino logic whereby a single clock cycle can be used to evaluate a relatively complex function.